How Many Registers Are Read In And Instruction Load Byte Instruction And Branch Instruction

Instruction Retentivity

Microarchitecture

David Money Harris , Sarah L. Harris , in Digital Design and Computer Architecture (Second Edition), 2013

vii.1.2 Blueprint Process

We will carve up our microarchitectures into ii interacting parts: the datapath and the command. The datapath operates on words of data. It contains structures such equally memories, registers, ALUs, and multiplexers. MIPS is a 32-bit architecture, then we will use a 32-fleck datapath. The control unit receives the current teaching from the datapath and tells the datapath how to execute that instruction. Specifically, the control unit produces multiplexer select, register enable, and memory write signals to command the functioning of the datapath.

A good way to design a complex arrangement is to start with hardware containing the land elements. These elements include the memories and the architectural country (the programme counter and registers). And so, add together blocks of combinational logic between the state elements to compute the new country based on the current land. The didactics is read from part of retentiveness; load and shop instructions then read or write data from another office of retentivity. Hence, information technology is often convenient to partition the overall retention into two smaller memories, one containing instructions and the other containing data. Figure 7.1 shows a block diagram with the four state elements: the program counter, register file, and pedagogy and data memories.

In Figure seven.one, heavy lines are used to indicate 32-flake data busses. Medium lines are used to indicate narrower busses, such as the 5-bit address busses on the annals file. Narrow blue lines are used to indicate command signals, such as the annals file write enable. Nosotros will use this convention throughout the chapter to avert cluttering diagrams with bus widths. Also, country elements usually have a reset input to put them into a known state at start-upwards. Again, to save clutter, this reset is not shown.

The program counter is an ordinary 32-bit register. Its output, PC, points to the current educational activity. Its input, PC′, indicates the accost of the adjacent instruction.

The instruction retentivity has a unmarried read port. ^one It takes a 32-bit pedagogy address input, A, and reads the 32-bit data (i.e., instruction) from that address onto the read data output, RD.

The 32-element × 32-bit annals file has two read ports and ane write port. The read ports take 5-bit address inputs, A1 and A2, each specifying one of 2⁵ = 32 registers every bit source operands. They read the 32-fleck annals values onto read data outputs RD1 and RD2, respectively. The write port takes a v-bit accost input, A3; a 32-bit write data input, WD; a write enable input, WE3; and a clock. If the write enable is 1, the register file writes the data into the specified register on the rising edge of the clock.

The information retentiveness has a single read/write port. If the write enable, WE, is one, it writes data WD into accost A on the ascent edge of the clock. If the write enable is 0, it reads address A onto RD.

Resetting the PC

At the very least, the plan counter must have a reset signal to initialize its value when the processor turns on. MIPS processors initialize the PC to 0xBFC00000 on reset and brainstorm executing code to start up the operating system (Os). The OS then loads an application plan at 0x00400000 and begins executing it. For simplicity in this chapter, we will reset the PC to 0x00000000 and place our programs there instead.

The education retentiveness, annals file, and data memory are all read combinationally. In other words, if the address changes, the new information appears at RD afterward some propagation delay; no clock is involved. They are written but on the rise edge of the clock. In this style, the state of the system is changed only at the clock border. The accost, data, and write enable must setup sometime before the clock edge and must remain stable until a agree fourth dimension after the clock edge.

Because the state elements change their state only on the rising edge of the clock, they are synchronous sequential circuits. The microprocessor is built of clocked country elements and combinational logic, then it too is a synchronous sequential circuit. Indeed, the processor tin can exist viewed equally a giant finite state auto, or as a drove of simpler interacting land machines.

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Case Study: System Design Using the Gumnut Core

Peter J. Ashenden , in The Designer's Guide to VHDL (Third Edition), 2008

22.one Overview of the Gumnut

The Gumnut is an viii-fleck processor core intended for educational purposes. (A gumnut is a small seedpod of an Australian eucalyptus tree. It is something small from which large things grow.) The Gumnut is like to 8-flake microcontrollers for small-scale embedded applications, merely has an instruction fix architecture more similar to RISC processors. We apply it as the subject of this case study to bear witness how we might develop high-level models of complex devices such every bit a CPU. Nosotros outset past describing the view of the processor equally seen by the machine language developer and past the hardware designer interfacing the processor with the rest of a computer system.

22.one.i Instruction Fix Architecture

The Gumnut has divide pedagogy and data memories. The teaching retention stores upwards to 4,096 instructions (using 12-bit addresses), and the data retentiveness stores 256 bytes (using 8-bit addresses). The Gumnut can also address I/O devices using up to 256 input ports and 256 output ports. Within the core, there are viii general-purpose registers, named r0 through r7, that can concur data to be operated upon by instructions. Register r0 is special, in that it is hardwired to have the value 0, and any updates to information technology are ignored. The processor too has two single-bit status-code registers called Z (nothing) and C (bear). They are set to 1 or cleared to 0 depending on the result of certain instructions, and can be tested to make up one's mind among alternative courses of action in the programme.

Table 22.1 lists the complete Gumnut instruction set in associates-language format. In the table, rd and rs are registers, op2 is a register ( rs2 ) or an immediate value ( immed ), count is count of number of places to shift or rotate, disp is a deportation from the next-instruction accost, and addr is a leap target address.

Table 22.one. The Gumnut instruction set

Arithmetic and logical instructions
add rd, rs, op2	Add rs and op2 , consequence in rd
addc rd, rs, op2	Add rs and op2 with carry, result in rd
sub rd, rs, op2	Subtract op2 from rs , consequence in rd
subc rd, rs, op2	Subtract op2 from rs with comport, effect in rd
and rd, rs, op2	Logical AND of rs and op2 , upshot in rd
or rd, rs, op2	Logical OR of rs and op2 , effect in rd
xor rd, rs, op2	Logical XOR of rs and op2 , result in rd
mask rd, rs, op2	Logical AND of rs and Not op2 , effect in rd
Shift instructions
shl rd, rs, count	Shift rs value left count places, result in rd
shr rd, rs, count	Shift rs value right count places, result in rd
rol rd, rs, count	Rotate rs value left count places, outcome in rd
ror rd, rs, count	Rotate rs value correct count places, result in rd
Retentiveness and I/O instructions
ldm rd, (rs)±offset	Load to rd from memory
stm rd, (rs)±offset	Store to memory from rd
inp rd, (rs)±first	Input to rd from input controller register
out rd, (rs)±outset	Output to output controller register from rd
Co-operative instructions
bz ± disp	Branch if Z is set
bnz ± disp	Branch is Z is not set
bc ± disp	Co-operative if C is set
bnc ± disp	Co-operative if C is not set
Jump instructions
jmp addr	Jump to addr
jsb addr	Jump to subroutine at addr
Miscellaneous instructions
ret	Return from subroutine
reti	Return from interrupt
enai	Enable interrupts
disi	Disable interrupts
wait	Expect for interrupts
stby	Enter low-ability standby mode

The arithmetic and logical instructions operate on viii-flake information values stored in the core's general-purpose registers and store the event in the destination register, rd . For each instruction, 1 value is taken from a source register, rs . The other value, op2 , either comes from a 2d source register ( rs2 ) or is an firsthand value ( immed ) specified every bit function of the teaching.

The add-on and subtraction instructions treat the data values as eight-bit unsigned integers. The addc instruction includes the value of the C condition code as a bear-in scrap, and the subc educational activity includes the C value as a borrow-in bit. All of the instructions in this group modify the Z and the C bits. They ready Z to ane if the instruction consequence is 0, and they clear Z to 0 if the result is non-zero. The add and addc instructions fix C to the acquit-out bit of the addition, the sub and subc instruction ready C to the borrow out of the subtraction, and the remaining logical instructions articulate C to 0.

The shift instructions shift or rotate 8-bit values taken from the full general purpose register rs and store the effect in annals rd . The number of places to shift or rotate is specified in the educational activity as count . The shift-left and shift-right instructions discard the bits shifted past the end of the 8-bit byte and fill up the vacated bit positions with 0s. The rotate-left and rotate-right instructions copy the bits shifted past the end of the byte around to the other end. All of these instructions set Z to 1 if the didactics result is 0, and they clear Z to 0 if the result is non-zero. They set the C flake to the value of the concluding bit shifted by the terminate of the byte.

The Gumnut has separate instructions and separate viii-bit address spaces for accessing data memory and I/O controllers. For all of the Gumnut's memory and I/O instructions, the address to access is computed by adding the electric current value in rs and an first value specified in the instruction. The load from memory education reads from the data memory at the computed address and puts the read value in register rd . The store to retentivity writes the value from register rd to the data memory at the computed address. The input and output instructions perform like operations, only read or write to the I/O controller registers at the computed address. None of these instructions affect the values of the Z and C bits.

If we desire to specify a particular address to admission, we can use r0 as the annals for rs . Recall that r0 e'er contains 0, and then adding it to the offset value specified in the education just gives the kickoff value. In this case, we usually interpret the beginning value as an unsigned 8-bit address. Our assembler tool allows us to imply the specification "(r0)" by omission and simply write the address value, for example,

inp r3, 156

which reads from the I/O controller annals at address 156 into r3. Similarly, if a register contains the address we want to access, nosotros can use an offset of 0. Again, our assembler allows united states to imply a 0 start by omission, as in the teaching

out r3, (r7)

The branch instructions modify the sequential catamenia of execution by irresolute value of the plan counter (PC) in the Gumnut core. Each form of branch tests a status, and if the status is true, adds a signed 8-bit displacement value to the PC. The displacement, specified in the didactics, indicates how many locations forward or astern the adjacent instruction to execute is from the current didactics. (A displacement of 0 refers to the instruction after the co-operative, since the PC has already been incremented after fetching the branch instruction.) If the condition is false, the PC is unchanged, and execution continues sequentially. The dissimilar co-operative instructions let united states of america to test each of the Z and C status lawmaking bits for being set up to 1 or not gear up to ane. Since these bits are affected by arithmetic, logical and shift instructions, we ofttimes deliberately precede a branch education with one of these instructions to compare data values. In other cases, the condition code setting occurs as a serendipitous side effect of information operations that we need to perform anyway. Execution of a branch instruction does not affect the values of the Z and C bits.

The get-go of the spring instructions, jmp, unconditionally breaks the sequential flow of execution by setting the PC to the address specified in the didactics. The second of the jump instructions, jsb, allows u.s.a. to call a subroutine. It is used in tandem with the ret instruction, which returns from the subroutine to the place of the phone call. The jsb pedagogy pushes the incremented PC value (the return address) onto an internal stack and and then updates the PC with the subroutine address specified in the instruction. The ret instruction pops the saved render address from the stack to the PC. The return-address stack tin can concur upwards to eight entries. The jmp and jsb instructions practise not touch on the values of the Z and C bits.

The remaining miscellaneous instructions deal with interrupts. The enable-interrupt (enai) instruction allows the processor to respond to interrupt events, and the disable-interrupt (disi) instruction prevents the processor from responding. When the processor responds to an interrupt consequence, it saves the incremented PC value and the values of the Z and C condition codes in special registers, disables further interrupts, and then transfers command to the interrupt handler at accost ane. The interrupt handler finishes with a render-from-interrupt (reti) educational activity rather than an ret pedagogy. The reti instruction restores the saved PC and condition lawmaking values and re-enables interrupts. The look instruction suspends execution until an interrupt occurs, and the stby didactics enters a low-power standby mode until an interrupt occurs. The difference is that the CPU would usually exist able to respond to an interrupt immediately when suspended using a expect instruction, whereas information technology could take some fourth dimension to power up from a stby didactics. The instructions in this group, apart from the reti pedagogy, practice not affect the values of the Z and C bits.

Instructions in the Gumnut are all 18 bits long, and are encoded in several formats, shown in Figure 22.i. The leftmost $.25, together with the function code (fn), form the opcode. The encoding used for function codes is shown in Table 22.2. Those instructions that specify register numbers accept the numbers encoded in 3-bit binary form in the rd, rs, and rs2 fields of the didactics discussion. Similarly, instructions that specify immediate values, offsets, or displacements accept those values binary encoded in the rightmost 8 $.25 of the didactics word. The shaded parts of the instruction discussion in each format correspond bits that are ignored.

Table 22.2. Office lawmaking values

add 000	addc 001	sub 010	subc 011
and 100	or 101	xor 110	mask 111
shl 00	shr 01	rol ten	ror 11
ldm 00	stm 01	inp x	out xi
bz 00	bnz 01	bc 10	bnc 11
jmp 0	jsb one
ret 000	reti 001	enai 010	disi 011
wait 100	stby 101

22.1.2 External Interface

The Gumnut interfaces to the residuum of the system in which it is embedded via a number of external signals. These are shown in Figure 22.2 . Each of the educational activity retention, information retentivity, and I/O ports connect to the core using a simplified version of the Wishbone autobus, an open bus specification published by the OpenCores Organization [13]. The clk_i signal is the master clock for the Gumnut. All other signals are sampled or set synchronously with the clock. The rst_i betoken re-initializes the Gumnut to its reset state. When rst_i is negated, the Gumnut commences didactics execution, starting from address 0 in the pedagogy memory.

The int_req signal is used to request an interrupt of the Gumnut. When this betoken is active and the Gumnut interrupts are enabled, the Gumnut volition save land and transfer to the interrupt service code. It asserts the int_ack signal for ane cycle to indicate start of interrupt service. The I/O port controller must negate int_req before the service code returns and re-enables interrupts; otherwise a second spurious interrupt will be received. Usually, an I/O port controller would negate the interrupt request in response to int_ack or to the Gumnut reading or writing an I/O port register.

Nosotros will describe the omnibus timing for read and write operations on the data retention passenger vehicle. The timing for reads and writes on the port coach and for reads on the didactics memory bus is identical. The timing of read operations is shown in Figure 22.3. The Gumnut starts a read operation by driving the data_adr_o signals with the address and setting data_cyc_o and data_stb_o to 1. It also sets data_we_o to 0 to indicate that the operation is a read. The retention decodes the accost to admission the data and drives the data onto the data_dat_i signal. If the retentivity is able to provide the data within the offset clock cycle, it sets the data_ack_i signal to one in that cycle, as shown in Figure 22.3(a). On the next rising clock-edge, the Gumnut sees data_ack_i at 1 and completes the operation by setting data_cyc_o, data_stb_o and data_we_o all to 0. If, on the other hand, the memory is tiresome and is non able to provide the data inside the cycle, it leaves data_ack_i at 0, as shown in Figure 22.3(b). The Gumnut sees data_ack_i at 0 on the rising clock-edge, and extends the performance for a further cycle. The retention can continue data_ack_i at 0 for as long as it needs to admission the data. Somewhen, when it is ready, information technology drives data_ack_i to ane to consummate the performance.

The timing of write operations is similar, shown in Figure 22.4. Again, the Gumnut starts a write functioning by driving the data_adr_o signal with the address and setting data_cyc_o and data_stb_o to 1. It sets data_we_o to 1 to point that the operation is a write and drives the data to exist written into the data_dat_o signal. The memory decodes the address and updates the selected location with the data. If the retention is able to consummate the write within the first clock bike, it sets the data_ack_i signal to 1 in that cycle, as shown in Figure 22.4(a), and the handshake completes equally for the read operation. Otherwise, if the memory is tedious, it leaves data_ack_i at 0, as shown in Figure 22.four(b), and the functioning is extended, as for a read operation.

At get-go sight, it might appear that the data_cyc_o and data_stb_o signals are duplicates of each other. However, the Wishbone passenger vehicle specification defines other more than involved operations in which the two control signals serve singled-out purposes. While the Gumnut does not use those operations, it includes the signals in social club to maintain compatibility with the Wishbone specification. The additional signal is a small cost to pay for compatibility with a large pool of third-political party components.

The Gumnut Entity Declaration

We can at present write the entity declaration for the Gumnut cadre, every bit shown beneath. The generic constant debug controls whether the model writes debugging letters to the standard output stream. The ports of the entity correspond to those shown in Figure 22.2.

library ieee;

utilize ieee.std_logic_1164.all, ieee.numeric_std.all;

entity gumnut is

generic ( debug : boolean := false );

port ( clk_i : in std_ulogic;

rst_i : in std_ulogic;

-- Instruction retentivity bus

inst_cyc_o : out std_ulogic;

inst_stb_o : out std_ulogic;

inst_ack_i : in std_ulogic;

inst_adr_o : out unsigned(11 downto 0);

inst_dat_i : in std_ulogic_vector(17 downto 0);

-- Data memory passenger vehicle

data_cyc_o : out std_ulogic;

data_stb_o : out std_ulogic;

data_we_o : out std_ulogic;

data_ack_i : in std_ulogic;

data_adr_o : out unsigned(seven downto 0);

data_dat_o : out std_ulogic_vector(7 downto 0);

data_dat_i : in std_ulogic_vector(7 downto 0);

-- I/O port bus

port_cyc_o : out std_ulogic;

port_stb_o : out std_ulogic;

port_we_o : out std_ulogic;

port_ack_i : in std_ulogic;

port_adr_o : out unsigned(7 downto 0);

port_dat_o : out std_ulogic_vector(7 downto 0);

port_dat_i : in std_ulogic_vector(7 downto 0);

-- Interrupts

int_req : in std_ulogic;

int_ack : out std_ulogic );

terminate entity gumnut;

Instruction and Data Memories

In systems that use the Gumnut core, we need to provide instruction and information memories. We can provide them as further IP blocks to be instantiated in designs. The entity declaration for the instruction memory is

library ieee;

apply ieee.std_logic_1164.all, ieee.numeric_std.all;

entity inst_mem is

generic ( IMem_file_name : string := "gasm_text.dat" );

port ( clk_i : in std_ulogic;

cyc_i : in std_ulogic;

stb_i : in std_ulogic;

ack_o : out std_ulogic;

adr_i : in unsigned(11 downto 0);

dat_o : out std_ulogic_vector(17 downto 0) );

end entity inst_mem;

The generic abiding IMem_file_name specifies the proper name of a file from which program is loaded. The default file name used by gasm is gasm_text.dat, so we use the same default name for the generic constant. The ports of the entity mirror those of the Gumnut entity.

The entity declaration for the data retention is like:

library ieee;

employ ieee.std_logic_1164.all, ieee.numeric_std.all;

entity data_mem is

generic ( DMem_file_name : cord := "gasm_data.dat" );

port ( clk_i : in std_ulogic;

cyc_i : in std_ulogic;

stb_i : in std_ulogic;

we_i : in std_ulogic;

ack_o : out std_ulogic;

adr_i : in unsigned(seven downto 0);

dat_i : in std_ulogic_vector(seven downto 0);

dat_o : out std_ulogic_vector(vii downto 0) );

terminate entity data_mem;

Once more, the entity has a generic for specifying the file proper name for the initial retention contents, and ports that mirror those of the Gumnut entity. We don't testify the architecture bodies for the memories here, in the interest of brevity. They are based on the memory models we described in Chapter 17.

Next, nosotros provide a subsystem model that includes an case of the core and each of the memories. This subsystem can and then exist instantiated in a larger design and continued to the required I/O controllers. The subsystem entity declaration is

library ieee;

utilize ieee.std_logic_1164.all, ieee.numeric_std.all;

entity gumnut_with_mem is

generic ( IMem_file_name : string := "gasm_text.dat";

DMem_file_name : cord := "gasm_data.dat";

debug : boolean := imitation );

port ( clk_i : in std_ulogic;

rst_i : in std_ulogic;

-- I/O port bus

port_cyc_o : out std_ulogic;

port_stb_o : out std_ulogic;

port_we_o : out std_ulogic;

port_ack_i : in std_ulogic;

port_adr_o : out unsigned(vii downto 0);

port_dat_o : out std_ulogic_vector(7 downto 0);

port_dat_i : in std_ulogic_vector(seven downto 0);

-- Interrupts

int_req : in std_ulogic;

int_ack : out std_ulogic );

end entity gumnut_with_mem;

The structural architecture body is shown below. It uses component declarations for the Gumnut core and the memories, allowing alternative compages bodies to be bound using a separate configuration annunciation.

library ieee;

employ ieee.std_logic_1164.all, ieee.numeric_std.all;

architecture struct of gumnut_with_mem is

-- Instruction retentivity bus

signal inst_cyc_o : std_ulogic;

signal inst_stb_o : std_ulogic;

signal inst_ack_i : std_ulogic;

signal inst_adr_o : unsigned(eleven downto 0);

point inst_dat_i : std_ulogic_vector(17 downto 0);

-- Data memory charabanc

indicate data_cyc_o : std_ulogic;

betoken data_stb_o : std_ulogic;

signal data_we_o : std_ulogic;

betoken data_ack_i : std_ulogic;

signal data_adr_o : unsigned(7 downto 0);

signal data_dat_o : std_ulogic_vector(7 downto 0);

signal data_dat_i : std_ulogic_vector(7 downto 0);

component gumnut is

generic ( debug : boolean );

port ( clk_i : in std_ulogic;

rst_i : in std_ulogic;

-- Didactics memory motorcoach

inst_cyc_o : out std_ulogic;

inst_stb_o : out std_ulogic;

inst_ack_i : in std_ulogic;

inst_adr_o : out unsigned(11 downto 0);

inst_dat_i : in std_ulogic_vector(17 downto 0);

-- Data memory bus

data_cyc_o : out std_ulogic;

data_stb_o : out std_ulogic;

data_we_o : out std_ulogic;

data_ack_i : in std_ulogic;

data_adr_o : out unsigned(7 downto 0);

data_dat_o : out std_ulogic_vector(vii downto 0);

data_dat_i : in std_ulogic_vector(seven downto 0);

-- I/O port bus

port_cyc_o : out std_ulogic;

port_stb_o : out std_ulogic;

port_we_o : out std_ulogic;

port_ack_i : in std_ulogic;

port_adr_o : out unsigned(7 downto 0);

port_dat_o : out std_ulogic_vector(7 downto 0);

port_dat_i : in std_ulogic_vector(7 downto 0);

-- Interrupts

int_req : in std_ulogic;

int_ack : out std_ulogic );

end component gumnut;

component inst_mem is

generic ( IMem_file_name : cord );

port ( clk_i : in std_ulogic;

cyc_i : in std_ulogic;

stb_i : in std_ulogic;

ack_o : out std_ulogic;

adr_i : in unsigned(11 downto 0);

dat_o : out std_ulogic_vector(17 downto 0) );

end component inst_mem;

component data_mem is

generic ( DMem_file_name : cord );

port ( clk_i : in std_ulogic;

cyc_i : in std_ulogic;

stb_i : in std_ulogic;

we_i : in std_ulogic;

ack_o : out std_ulogic;

adr_i : in unsigned(7 downto 0);

dat_i : in std_ulogic_vector(7 downto 0);

dat_o : out std_ulogic_vector(seven downto 0) );

stop component data_mem;

begin

core : component gumnut

generic map ( debug => debug )

port map ( clk_i => clk_i,

rst_i => rst_i,

inst_cyc_o => inst_cyc_o,

inst_stb_o => inst_stb_o,

inst_ack_i => inst_ack_i,

inst_adr_o => inst_adr_o,

inst_dat_i => inst_dat_i,

data_cyc_o => data_cyc_o,

data_stb_o => data_stb_o,

data_we_o => data_we_o,

data_ack_i => data_ack_i,

data_adr_o => data_adr_o,

data_dat_o => data_dat_o,

data_dat_i => data_dat_i,

port_cyc_o => port_cyc_o,

port_stb_o => port_stb_o,

port_we_o => port_we_o,

port_ack_i => port_ack_i,

port_adr_o => port_adr_o,

port_dat_o => port_dat_o,

port_dat_i => port_dat_i,

int_req => int_req,

int_ack => int_ack );

core_inst_mem : component inst_mem

generic map ( IMem_file_name => IMem_file_name )

port map ( clk_i => clk_i,

cyc_i => inst_cyc_o,

stb_i => inst_stb_o,

ack_o => inst_ack_i,

adr_i => inst_adr_o,

dat_o => inst_dat_i );

core_data_mem : component data_mem

generic map ( DMem_file_name => DMem_file_name )

port map ( clk_i => clk_i,

cyc_i => data_cyc_o,

stb_i => data_stb_o,

we_i => data_we_o,

ack_o => data_ack_i,

adr_i => data_adr_o,

dat_i => data_dat_o,

dat_o => data_dat_i );

end architecture struct;

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Microarchitecture

Sarah L. Harris , David Harris , in Digital Design and Figurer Architecture, 2022

R-Type Instructions

Next, consider extending the datapath to handle the R-blazon instructions, add together, sub, and, or, and slt. All of these instructions read ii source registers from the register file, perform some ALU operation on them, and write the result back to the destination register. They differ but in the specific ALU operation. Hence, they tin can all be handled with the same hardware simply with different ALUControl signals. Recall from Section v.ii.four that ALUControl is 000 for add-on, 001 for subtraction, 010 for AND, 011 for OR, and 101 for set less than.

Figure 7.10 shows the enhanced datapath treatment these R-type instructions. The datapath reads rs1 and rs2 from ports 1 and two of the register file and performs an ALU performance on them. Nosotros innovate a multiplexer and a new select signal, ALUSrc, to select between ImmExt and RD2 as the second ALU source, SrcB. For lw and sw, ALUSrc is 1 to select ImmExt; for R-type instructions, ALUSrc is 0 to select the register file output RD2 as SrcB.

Let us name the value to be written back to the register file Effect. For lw, Result comes from the ReadData output of the retentivity. Still, for R-type instructions, Upshot comes from the ALUResult output of the ALU. We add the Result multiplexer to choose the proper Result based on the type of education. The multiplexer select betoken ResultSrc is 0 for R-type instructions to choose ALUResult equally Result; ResultSrc is 1 for lw to choose ReadData. We do not care most the value of ResultSrc for sw because information technology does not write the register file.

In our example, the PC is 0x1008. Thus, the instruction memory reads out the or didactics 0x0062E233. The annals file reads source operands half-dozen from x5 and x from x6. ALUControl is 011, so the ALU computes 6 | 10 = 0110₂ | 1010₂ = 1110₂ = 14. The result is written dorsum to x4. Meanwhile, the PC is incremented to 0x100C.

Detect that our hardware computes all the possible answers needed past dissimilar instructions (eastward.g., ALUResult and ReadData) and so uses a multiplexer to choose the advisable 1 based on the teaching. This is an of import design strategy. Throughout the balance of this chapter, we will add multiplexers to choose the desired respond.

One of the major differences between software and hardware is that software operates sequentially, so we can compute only the answer we demand. Hardware operates in parallel; therefore, we often compute all the possible answers and so choice the ane we demand. For example, while executing an R-type instruction with the ALU, the memory still receives an address and reads data from this address even though we don't care what that data might be.

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Instruction Sets

Marilyn Wolf , in Computers as Components (Fourth Edition), 2017

2.4.ii Information operations

The PIC16F family unit uses a 13-bit program counter. Different members of the family provide dissimilar amounts of instruction or data memory: 2K instructions for the depression-finish models, 4K for medium, and 8K for large.

Pedagogy infinite

Fig. 2.eighteen shows the organization of the education infinite. The programme counter can exist loaded from a stack. The lowest addresses in memory hold the interrupt vectors. The remainder of memory is divided into iv pages. The low-end devices take access only to page 0; the medium-range devices accept admission only to pages 1 and two; loftier-stop devices accept admission to all iv pages.

Information space

The PIC16F data memory is divided into iv $.25. Two $.25 of the Condition annals, RP<one:0>, select which banking concern is used. Moving-picture show documentation uses the term general-purpose annals to mean a data memory location. It too uses the term file register to refer to a location in the general-purpose register file. The lowest 32 locations of each bank contain special function registers that perform many different operations, primarily for the I/O devices. The rest of each bank contains full general-purpose registers.

Because different members of the family support different amounts of data memory, non all of the bank locations are available in all models. All models implement the special role registers in all banks. Simply not all of the banks make available to the developer their general-purpose registers. The low-end models provide general-purpose registers merely in bank 0, the medium models simply in banks 0 and 1, while the high-end models support general-purpose registers in all four banks.

Plan counter

The 13-chip plan counter is shadowed by two other registers: PCL and PCLATH. $.25 PC<seven:0> come from PCL and can be modified directly. Bits PC<12:8> of PC come from PCLATH which is not straight readable or writable. Writing to PCL will ready the lower bits of PC to the operand value and set the high $.25 of PC from PCLATH.

PC stack

An eight-level stack is provided for the program counter. This stack space is in a split address infinite from either the program or data retentivity; the stack pointer is not straight attainable. The stack is used by the subroutine Telephone call and Return/RETLW/RETFIE instructions. The stack actually operates equally a circular buffer—when the stack overflows, the oldest value is overwritten.

STATUS register

STATUS is a special function register located in bank 0. Information technology contains the status bits for the ALU, reset status, and banking company select $.25. A variety of instructions can affect bits in STATUS, including deport, digit bear, zero, register bank select, and indirect register bank select.

Addressing modes

Moving-picture show uses f to refer to one of the general-purpose registers in the register file. W refers to an accumulator that receives the ALU result; b refers to a fleck address inside a register; k refers to a literal, abiding, or characterization.

Indirect addressing is controlled past the INDF and FSR registers. INDF is not a concrete register. Whatever access to INDF causes an indirect load through the file select register FSR. FSR can be modified as a standard register. Reading from INDF uses the value of FSR as a pointer to the location to be accessed.

Information instructions

Fig. 2.19 lists the data instructions in the PIC16F. Several different combinations of arguments are possible: ADDLW adds a literal k to the accumulator W; ADDWF adds West to the designated register f.

Example 2.7 shows the code for an FIR filter on the PIC16F.

Example 2.7 FIR Filter on the PIC16F

Here is the code generated for our FIR filter by the PIC MPLAB C32 compiler, along with some manually generated comments. Every bit with the ARM, the PIC16F uses a stack frame to organize variables:

.L2:

lw $2,0($fp)

slt $ii,$two,viii

beq $2,$0,.L3 ; loop test---done?

nop ; fall through conditional branch

here

lw $2,0($fp)

sll $ii,$ii,2 ; compute address of starting time array

value

addu $iii,$two,$fp

lw $two,0($fp)

sll $two,$ii,2 ; compute address of 2d assortment

value

addu $two,$2,$fp

lw $3,viii($3) ; get first assortment value

lw $2,xl($two) ; get second array value

mul $3,$three,$two ; multiply

lw $two,iv($fp)

addu $two,$ii,$3 ; add together to running sum

sw $ii,4($fp) ; store result

lw $2,0($fp)

addiu $2,$2,1 ; increment loop count

sw $2,0($fp)

b .L2 ; unconditionally go dorsum to the

loop test

nop

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Digital Signal Processors

James D. Broesch , in Digital Betoken Processing, 2009

Architecture

DSP chips often have a Harvard-type architecture (see Effigy eight.3) or some modified version of Harvard compages. This type of system compages implies that at that place are at least two system buses, 1 for instruction transfers and one for data. Quite often, 3 system buses tin be constitute on DSPs, one for instructions, one for data (including I/O) and one for transferring coefficients from a split memory surface area or chip.

In this way, when running an FIR filter algorithm like in Equation 8.2, instructions can be fetched at the same time as data from the filibuster line x(n−thou) is fetched and as filter coefficients b_grand are fetched from coefficient retentiveness. Hence, using a DSP for the 10-tap FIR filter, only 12 charabanc cycles will be needed including pedagogy and data transfers.

Many DSP fries as well have internal memory areas that can exist allocated as data memory, coefficient retentiveness and/or instruction memory, or combinations of these. Pipelining is used in about DSP fries.

Alert!

Some DSP chips execute instructions in the pipeline in a parallel, "smart" fashion to increase speed. The consequence volition in some cases be that instructions volition non exist executed in the same order every bit written in the plan code. This may of course lead to foreign beliefs and cumbersome troubleshooting. One style to avoid this is to insert "dummy" instructions (for instance, no operation (NOP)) in the program code in the critical parts (consult the information sheet of the DSP chip to find out about pipeline latency). This will of course increase the execution fourth dimension.

The execution unit of measurement consists of at least one (often two) arithmetic logic unit (ALU), a multiplier, a shifter, accumulators, and information and flag registers. The unit of measurement is designed with a high degree of parallelism in mind, hence all the ALUs, multipliers, etc., can be run simultaneously. Further, ALUs, the multiplier and accumulators are organized so that the MAC operation tin can be performed as efficiently as possible with the use of a minimum amount of internal data movements. Stock-still-point DSPs handle two's complement arithmetic and binary fractions format. Floating-point DSPs use floating-signal formats that can be IEEE standard or some other non-standard format. In many cases, the ALUs can too handle both wrap-around and saturation arithmetic which will be discussed later in this chapter.

Many DSPs also have ready-fabricated await-upward tables (LUT) in memory (read just retentiveness (ROM)). These tables may be A-law and/or μ-law for companding systems and/or sine/cosine tables for FFT or modulation purposes.

Different conventional processors having 16-, 32- or 64-bit double-decker widths, DSPs may accept uncommon charabanc widths like 24, 48 or 56 $.25, etc. The width of the pedagogy passenger vehicle is called such that an RISC-like system can be accomplished, i.eastward. every instruction only occupies ane memory discussion and tin can hence be fetched in 1 bus bicycle. The information buses are given a motorcoach width that can handle a word of appropriate resolution, at the same time as extra high bits are nowadays to keep overflow bug nether control.

The accost unit is complicated since it may be expected to run iii address buses in parallel. There is of course a plan counter and a stack pointer as in a conventional processor, just nosotros are besides likely to find a number of index and pointer registers used to generate data retention addresses. Quite often there is as well one or 2 ALUs for calculating addresses when accessing filibuster lines (vectors in data memory) and coefficient tables. These arrow registers tin often be incremented or decremented in a modulo fashion, which for instance simplifies building circular buffers. The AU may also be able to generate the specific bit reverse operations used when addressing butterflies in FFT algorithms.

Further, in some DSPs, the stack is implemented as a split last in first out (LIFO) register file in silicon ("hardware stack"). Using this approach, pushing and popping on the stack will exist faster, and no address bus will be used.

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High-operation embedded computing

João M.P. Cardoso , ... Pedro C. Diniz , in Embedded Computing for High Performance, 2017

2.2.2 Multiprocessor and Multicore Architectures

Modern microprocessors are based on multicore architectures consisting of a number of processing cores. Typically, each core has its ain instruction and information memories (L1 caches) and all cores share a second level (L2) on-chip cache. Fig. two.4 presents a block diagram of a typical multicore (a quad-core in this example) CPU calculating system where all cores share an L2 cache. The CPU is also connected to an external memory and includes link controllers to access external system components. There are, however, multicore architectures where one L2 cache is shared by a subset of cores (e.thousand., each L2 cache is shared by two cores in a quad-cadre, or is shared by 4 cores in an octa-cadre CPU). This is common in computing systems with additional memory levels. The external memories are often grouped in multiple levels and utilize unlike storage technologies. Typically, the first level is organized using SRAM devices, whereas the second level uses DDRAMs.

Combining CPUs With FPGA-Based Accelerators

Several platforms provide FPGA-based hardware extensions to article CPUs. Examples include the Intel QuickAssist QPI-FPGA [10], IBM Netezza [11], CAPI [12], and Xilinx Zynq [13]. Other platforms, such every bit Riffa [14], focus on vendor-independent back up by providing an integration framework to interface FPGA-based accelerators with the CPU arrangement charabanc using the PCI Express (PCIe) links.

Other system components, such every bit GPIO, UART, USB interface, PCIe, network coprocessor, and power manager, are connected via a fast link perhaps beingness memory mapped. In other architectures, however, the CPU connects to these subsystems (including memory) exclusively using fast links and/or switch fabrics (eastward.g., via a partial crossbar), thus providing betoken-to-signal communication channels betwixt the architecture components.

In computing systems requiring higher performance demands, it is mutual to include more than than one multicore CPU (e.g., with all CPUs integrated every bit a CMP ¹ ). Figs. 2.5 and two.half-dozen illustrate two possible organizations of CMPs, one using a distributed memory organization (Fig. two.5) and another one using a shared retentivity organization (Fig. two.6).

Fig. 2.v presents an example of a nonuniform memory access architecture (NUMA). In such systems, the distributed memories are viewed as one combined retentivity by all CPUs; however, access times and throughputs differ depending on the location of the memory and the CPU. For instance, the memory accesses of the CPU located at the opposite side of where the target memory is located incurs in a larger latency than the accesses to a nearby memory.

CPUs as well provide parallel execution back up for multiple threads per core. Systems with more i multicore CPU accept the potential to take many concurrently executing threads, thus supporting multithreaded applications.

Virtually Interconnection of the CPUs and Other Components

The blazon of interconnections used in a target architecture depends on the level of performance required and the platform vendor.

An example of a switch fabric is the TeraNet, ^a and an case of a fast link is HyperLink. ^a They are both used in some ARM-based SoCs proposed by Texas Instruments Inc, ^a providing efficient interconnections of the subsystems to the ARM multicore CPUs and to the external accelerators.

In Intel-based computing systems, the retentiveness subsystem is usually connected via Intel Scalable Memory Interfaces (SMI) provided by the integrated memory controllers in the CPU. They also include a fast link connecting other subsystems to the CPU using the Intel QuickPath Interconnect (QPI), ^b a indicate-to-signal interconnect technology. AMD provides the HyperTransport ^c applied science for signal-to-indicate links.

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Dataflow Processing

Krishna Kavi , ... Domenico Pace , in Advances in Computers, 2015

4.4 Explicit Token Shop

The problems described higher up have led to the introduction of the explicit token store (ETS) model. Storage (called activation frames) is allocated dynamically for all the tokens that can be generated by a code block (a code block represents a function or a loop iteration). The utilization of retentivity locations is defined at compile fourth dimension, while memory resource allotment takes place directly at runtime. A lawmaking block is represented by the pair <FP, IP>, called a continuation, where FP is the pointer to the activation frame and IP is prepare initially to the first statement in the block. A typical instruction specifies the opcode, an offset within the activation frame where it checks the availability of inputs and one or more offsets, chosen displacements, which define the instructions that volition receive the event calculated past the node. Each deportation too has an associated indicator (left/right) that specifies whether the issue will be the left or correct operand of the destination instruction. Figure 14 shows an example of lawmaking cake invocation with its teaching memory and frame memory.

When a token arrives at a node, in this example the node Add together, the IP points to the relative education in the instruction retentiveness. The system executes the procedure of comparing the inputs in the slot that is specified by FP + r. If the slot is empty, the system writes the value in the slot and sets the presence bit to indicate that the slot is full. If the presence scrap is already ready, it means that one of the ii operands of the instruction is already available, and so the organization can now execute the instruction. The steps that the system performs are as follows:

•: extract the value, leaving the slot empty and complimentary;
•: perform the operation of the instruction;
•: communicate the result token to the destination instructions according to the displacement; and
•: update the teaching pointer.

For example, once the ADD educational activity is completed, two tokens are generated: 1 is directed to the education NEG with token <FP, IP + i, 3.55> and the other is directed to the instruction SUB with token <FP, IP + ii, 3.55>.

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Teaching Sets

Marilyn Wolf , in Computers as Components (Third Edition), 2012

2.4.1 Processor and Memory Organization

The PIC16F family has a Harvard architecture with separate information and plan memories. Models in this family take up to 8,192 words of instruction memory held in wink. An instruction word is 14 bits long. Information memory is byte addressable. They may have upward to 368 bytes of data memory in static random-access memory (SRAM) and 256 bytes of electrically-erasable programmable read-but memory (EEPROM) data memory.

Members of the family provide several low power features: a sleep manner, the ability to select different clock oscillators to run at different speeds, and then on. They also provide security features such as code protection and component identification locations.

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Operation Estimation of Embedded Software with Educational activity Cache Modeling

YAU-TSUN STEVEN LI , ... ANDREW WOLFE , in Readings in Hardware/Software Co-Design, 2002

2 RELATED Work

The problem of finding a program's worst-case execution time is in general undecidable and is equivalent to a halting problem. This is truthful even with a abiding-admission-time teaching retentiveness. Kligerman and Stoyenko [1986], as well as Puschner and Koza [1989], listed the conditions for this problem to exist decidable. These conditions are bounded loops, absenteeism of recursive part calls, and absence of dynamic role calls. These researchers, together with Mok et al. [1989] and Park and Shaw [1992], have proposed a number of methods to determine the estimated WCET. These methods assume a simple hardware model such that the execution time of every instruction in the program is a constant equal to the instruction'south worst-case execution time. No cache assay is performed.

The presence of enshroud memory complicates the WCET analysis significantly. The reason is that to determine the worst-case execution path, the execution times of individual instructions are needed. Nevertheless without knowing the worst-case execution path, the cache hits and misses of instructions, and hence the execution times of the instructions, cannot be adamant. As a event, program path assay and enshroud memory analysis are interrelated.

Several WCET analyses with straight-mapped pedagogy enshroud modeling methods have recently been proposed. Liu and Lee [1994] noted that a sufficient condition for determining the exact worst-case enshroud behavior is to search through all feasible program paths exhaustively. This becomes an intractable problem whenever there is a conditional statement within a while loop, which unfortunately happens oft. Lim et al. [1994], who extended Shaw'due south timing schema methodology [Shaw 1989] to incorporate cache analysis, as well encountered a like problem. To bargain with this intractable problem, the above researchers merchandise-off cache prediction accuracy for computational complexity by proposing dissimilar pessimistic heuristics. Fifty-fifty so, the size of the program for analysis is still limited. Arnold et al. [1994] proposed a less ambitious cache analysis method. They used flow assay to identify the potential cache conflicts and classified each instruction as outset miss, always striking, always miss, or kickoff hit categories. This results in fast but less authentic enshroud assay. Rawat [1993] handled data cache performance analysis past using graph-coloring techniques. Yet, this arroyo had limited success fifty-fifty for small programs. A severe drawback of all the methods above is that they exercise not take whatsoever user annotations describing infeasible program paths, which are essential in tightening the estimated WCET.

Explicit path enumeration is not a necessity in obtaining a tight estimated WCET. An important observation hither is that the WCET tin can be computed by methods other than path enumeration. We propose a method that determines the worst-example execution counts of the instructions and, from these counts, computes the estimated WCET. The primary advantage of this method is that information technology reduces the solution search space significantly. Further, equally we prove in Section four, just minimal necessary sequencing information is kept in performing the cache assay. No path enumeration is needed. The method supports user annotations that is at to the lowest degree as powerful as Park'south Information Description Linguistic communication (IDL) [Park 1992] and, at the same time, computes the enshroud memory activity that is far more accurate than Lim'due south work. To the best of our cognition, our inquiry is the first to address both issues together.

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Traditional microarchitectures

Shigeyuki Takano , in Thinking Machines, 2021

2.ane.2.2 Concept of programming model on microprocessors

Fig. 2.3(a) shows the pseudo code of a program (upside) and its assembly code (bottom). The program uses arrays and a for-loop.

The array is translated into 2 alphabetize values, namely, a base address of the information retentiveness and a position index (an showtime) indicating the position from the base of operations address. An assembly, a binary instruction, is fetched from the instruction retentivity to the instruction annals (IR) using a program counter (PC), i.e., a Harvard architecture, which decouples the instruction and information address infinite to each, as shown in Fig. 2.three(b). The instruction decoder decodes the IR value to the prepare of control signals. The betoken decides which operation should be operated, the location of the source operands in the RF, and where the destination operand is located to store its performance result.

A typical basic block has a jump or co-operative instruction at stop of the basic block. A for-loop is translated into a repeat-time adding, the instruction is compared to cheque the repeating fourth dimension on the loop achieved to exit from the loop, and a conditional co-operative with a branch teaching is and so applied, equally shown at the lesser of Fig. ii.3(a). The comparing outcome is stored in a control status annals (CSR), and the following branch didactics determines the next basic block based on the CSR value. The PC is updated with an commencement value greater than 1 or less than −1 if the condition is true; thus, the co-operative makes a conditional co-operative to jump onto the educational activity retentivity address.

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